1. Field of the Invention
The present invention relates to an image pickup sensor, a driving method therefor, and an image pickup apparatus.
2. Description of the Related Art
For image pickup apparatuses such as digital cameras and video cameras, a solid-state image pickup device such as a CMOS image sensor is widely used as an image pickup sensor.
In recent years, a solid-state image pickup device has increased in the number of pixels, and the size of each pixel has been made small. However, as the pixel size decreases, the quantity of light incident on each pixel decreases, and therefore, pixels are likely to be affected by noise, bringing about degradation in image quality.
A description will now be given of a principle on which the noise is generated with reference to FIGS. 8 and 9. FIG. 8 is a circuit diagram schematically showing an arrangement of a pixel in a CMOS image sensor (hereinafter referred to as a “CMOS sensor”). Each pixel in the CMOS sensor has a photodiode PD that converts photoelectrons into electrical charges (signal electrical charges) and accumulates the same, and a transfer switch M1 that transfers signal electrical charges accumulated in the photodiode PD to a floating diffusion FD.
Each pixel mentioned above also has an amplification MOS transistor M3 that converts signal electrical charges in the floating diffusion FD into voltage and amplifies the same, a reset switch M2 that resets signal electrical charges in the photodiode PD and the floating diffusion FD. Turning-on/off of the reset switch M2 is controlled by a pixel reset signal PRES from a vertical scanning circuit 93 (see FIG. 9). Further, each pixel mentioned above has a row selection switch M4.
A description will now be given of how signal electrical charges generated and accumulated in the photodiode PD are scanned. In a given nth row in a pixel group 90, first, a reset operation is carried out in which a pixel reset signal PRES and a transfer signal PTX are applied from the vertical scanning circuit 93 to turn on the transfer switches M1 and the reset switches M2, and unnecessary electrical charges accumulated in the photodiodes PD and the floating diffusions FD in the nth row are removed. Next, an accumulating operation is started in which the transfer switches M1 are turned off to start the accumulation of signal electrical charges generated in the photodiodes PD. Then, a transfer operation is carried out in which a transfer signal PTX is applied from the vertical scanning circuit 93 to turn on the transfer switches M1, and the signal electrical charges accumulated in the photodiodes PD are transferred to the floating diffusions FD. After completion of the transfer operation in the nth row, a row selection signal PSEL is applied from the vertical scanning circuit 93 to collectively turn on the row selection switches M4 of the respective pixels in the nth row. As a result, the electrical charges accumulated in the floating diffusions FD of the respective pixels in the nth row are converted into voltages, which are then outputted all at once to a vertical signal line V.
FIG. 9 is a circuit diagram schematically showing an overall arrangement of the general CMOS sensor. The CMOS sensor has the pixel unit 90, the vertical scanning circuit 93, a line memory 94, and a horizontal scanning circuit 96. The pixel unit 90 is comprised of an effective pixel region 91 and a reference pixel region 92.
Signal electrical charges in the effective pixel region 92 are actually used as a picked-up image reflecting a subject, and signal electrical charges in the reference pixel region 92 are used as reference signals for obtaining image signals not dependent on a state of the subject. It should be noted that pixels in the reference pixel region 92 are comprised of light-blocking pixels shielded from light by light shield members such as metallic films, or non-photosensitive pixels that do not have photodiodes.
Among pixels arranged in a matrix in the pixel unit 90, the accumulation, vertical transfer, and resetting of signal charges in respective pixels arranged in the same row are controlled at the same time by a transfer signal PTX, a reset signal PRES, and a row selection signal PSEL from the vertical scanning circuit 93. Moreover, respective pixels arranged in the same columns are commonly connected to the same vertical output lines V1 to Vm−1, and the respective vertical output lines V1 to Vm−1 are connected to respective line memories C1 to Cm−1. The line memories C1 to Cm−1 are connected to a horizontal output line 95 via respective horizontal scanning switches Q1 to Qm−1.
The horizontal scanning switches Q1 to Qm−1 are controlled by the horizontal scanning circuit 96. The horizontal scanning circuit 96 has D flip-flops FF1 to FFm−1 connected to the respective horizontal scanning switches Q1 to Qm−1, and the respective D flip-flops FF1 to FFm−1 are connected in series in such a manner that Q output terminals and D input terminals are sequentially connected to each other. The D flip-flop FF will hereinafter be abbreviated as “DFF”.
Thus, when a horizontal scanning start pulse signal PHST is inputted to the D input terminal of DFF1 in the first stage, the horizontal scanning start pulse signal PHST is sequentially shift-transferred to DFF2 to DFFm−1 in the subsequent stages, so that the horizontal scanning switches Q1 to Qm−1 are sequentially turned on.
As a result, the signal electrical charges (also referred to as pixel signals) of the respective pixels arranged in the same row vertically transferred to the line memories C1 to Cm−1 are sequentially read out to the horizontal output line 95 and outputted to an image processing circuit 7 in a subsequent stage. On the other hand, each time a vertical scanning pulse signal PV, not shown, is inputted to the vertical scanning circuit 93, the vertical scanning circuit 93 shifts a pixel row to which a transfer signal PTX, a reset signal PRES, and a row selection signal PSEL are outputted to the next pixel row.
It should be noted that a power supply and a GND are shared by the respective pixels. For this reason, when a voltage level of the power supply and the GND changes during readout of signal electrical charges in a selected pixel row, a power level of the signal electrical charges in respective pixels in the selected pixel row changes all at once. In this case, when the voltage level of the power supply and the GND changes during scanning of one frame, horizontal-striped pattern noise arises in a picked-up image because an amount of change in the voltage level differs according to respective pixel rows.
If the amount of change in the voltage level of the power supply and the GND is not periodical but random in the individual selected rows, the horizontal-striped pattern noise also arises randomly. Examples of methods to correct for such horizontal-striped pattern noise include an offset correction in which an average value of noise voltages of pixels in individual rows in the reference pixel region is calculated, and the average value is subtracted from signal electrical charges in individual rows in the effective pixel region.
As a general image sensor, an image sensor in which a reference pixel region is provided adjacent to one of four sides of an effective pixel region, or an image sensor in which reference pixel regions are provided adjacent to perpendicular two sides of four sides of an effective pixel region is widely used. In such an image sensor, if the amount of change in the level of respective pixels in a selected pixel row is the same, the horizontal-striped pattern noise can be suitably corrected for by the offset correction using the average value of the noise voltages in the reference pixel region.
However, a wiring length from the power supply and the GND to individual pixels differs according to a layout of power lines and GND lines in the image sensor, and a wiring impedance differs according to pixels.
Namely, the longer the wiring length from the power supply and the GND to a pixel, the greater the wiring impedance on the pixel is, the more greatly the pixel is affected by variations in the voltage level of the power supply and the GND, and the higher the noise voltage is. Generally, in a case where the power supply and the GND are supplied from the left side in the image sensor, the wiring lengths to the right side pixels are longer, and the noise voltages thereof are higher. In other words, the noise voltage slopes upward or downward.
Thus, when the noise voltage differs according to the horizontal positions, if the offset correction using the average value of the noise voltages is carried out, only a low degree of effectiveness can be obtained in the effective pixel region away from a reference pixel region although a high degree of effectiveness can be obtained in the effective pixel region close to a reference pixel region.
To solve this problem, a CCD image pickup apparatus in which OB units (optical black units: reference pixel regions) are disposed above and below an effective pixel region, that is, on opposing two sides of the effective pixel region has been proposed in Japanese Laid-Open Patent Publication (Kokai) No. H06-078224.
In the COD image pickup apparatus disclosed in Japanese Laid-Open Patent Publication (Kokai) No. H06-078224, the noise voltage of the effective pixel region is calculated in an estimating manner based on the noise voltage of the OB units disposed adjacent to the opposing two sides of the effective pixel region, and the calculated noise voltage is subtracted from an image voltage signal to carry out a correction.
In this case, because the noise voltage used for the correction is obtained from the two OB units disposed adjacent to the opposing two sides of the effective pixel region, the correction can be more suitably carried out even in a case where the noise voltage changes in one readout direction.
In a case where the arrangement disclosed in Japanese Laid-Open Patent Publication (Kokai) No. H06-078224 specific to the CCD image pickup apparatus is applied to a CMOS sensor, an arrangement as shown in FIG. 10 can be envisaged. Specifically, a left OB unit (first reference pixel region) 1002a and a right OB unit (second reference pixel region) 1002b are disposed on, for example, horizontally opposing two sides of four sides of an effective pixel region 1001.
At each readout of pixel signals in one row (1H), noise components in the effective pixel region 1001 are estimated from pixel signals of the left and right OB units 1002a and 1002b, and respective pixel signals in the effective pixel region 1001 are corrected.
Referring now to a timing chart of FIG. 11, a detailed description will be given of scanning control in a case where a general method to scan pixel signals in a CMOS sensor is applied to the CMOS sensor shown in FIG. 10. It should be noted that in the exemplary arrangement of the CMOS sensor shown in FIG. 10, a horizontal scanning start pulse signal PHST is inputted from the left end of the CMOS sensor 1000.
In response to the input of a vertical scanning pulse signal PV, not shown, to a vertical scanning circuit 1003 (t1 to t2 in FIG. 11), a pixel row in which readout of pixel signals is to be carried out is selected. Various control signals, not shown, are transmitted as necessary from the vertical scanning circuit 1003 (t2 to t3), and pixel signals of respective pixels in the selected row are read out all at once and vertically transferred to and held in the line memories C1 to Cn in respective columns.
After that, when a horizontal scanning start pulse signal PHST is inputted as a horizontal scanning start signal to DFF1 (t3), first, an active pulse is outputted from DFF1 to a horizontal scanning switch Q1 in synchronization with the input of a horizontal scanning pulse PH (t4 to t6). As a result, the pixel signals held in the line memory C1 corresponding to the left-end pixel column are read out to a horizontal output line 1005 and horizontally transferred.
After that, the horizontal scanning start pulse signal PHST is shift-transferred to DFF2 to DFFn, whereby the pixel signals held in the line memories C2 to Cn corresponding to the respective pixel columns are read out in order to the horizontal output line 1005 and horizontally transferred in synchronization with the input of the horizontal scanning pulse PH (t6 to t12). At t13 and afterward, the same operation as at t1 to t12 is repeatedly carried out for the next and subsequent pixel rows, so that scanning of pixel signals in one frame is carried out.
It should be noted that in the present specification, the term “scanning” is used as a term encompassing both vertical scanning and horizontal scanning. The term “vertical scanning” is used as a term encompassing both readout of pixel signals from pixels and vertical transfer thereof. The term “horizontal scanning” is used as a term encompassing both readout of pixel signals from the line memories C1 to Cn and horizontal transfer thereof.
As described above, in the general pixel signal scanning method in the CMOS sensor, pixel signals in a selected pixel row are vertically transferred all at once and temporarily held in the line memories in respective columns. Then, the held pixel signals are sequentially read out to the horizontal output line and horizontally transferred from the line memory at one end toward the line memory at the other end.
In a case where a reference pixel region is disposed adjacent to one side of an effective pixel region, readout of pixel signals from the line memories is started from a column corresponding to the leading end of the pixel unit, so that pixel signals in the reference pixel region for the offset correction are read out before pixel signals in the effective pixel region.
Thus, in this case, at least while pixel signals in the reference pixel region are being read out, calculation of offset correction values can be started in the image processing circuit, and thereafter, the offset correction can be promptly carried out for the subsequently read-out pixel signals in the effective pixel region. Moreover, storage capacity of the image processing circuit required for the offset correction processing has only to be such a capacity as to store the pixel signals in the reference pixel region.
However, in a case where reference pixel regions are disposed adjacent to two opposing sides of an effective pixel region, and correction processing is carried out on signals in the reference pixel regions based on correction values calculated in an estimating manner using signals in all the disposed reference pixel regions, the correction processing cannot be efficiently carried out, and the storage capacity of the image processing circuit required for the correction processing must be large in the conventional pixel signal scanning method.
Namely, to properly carry out the correction processing based on noise voltages in the two reference pixel regions disposed adjacent to the two opposing sides of the effective pixel region, pixel signals in all the pixels in one row must be stored in the memory of the image processing circuit.
In other words, unless pixel signals in all the pixels in one row are stored in the memory of the image processing circuit, the correction processing cannot be started. Moreover, the storage capacity of the image processing circuit required for the correction processing has to be such a capacity as to store pixel signals in all the pixels in one row of the effective pixel region and the two reference pixel regions, which requires high cost.
In recent years, higher image quality, higher-speed continuous shooting, pickup of moving images, and so on have been demanded of image pickup apparatuses, and also, there has been an increasing demand to speed up the above described correction processing on noise components.